Memory devices typically store (write) and retrieve (read) data from a memory array based on an address. In conventional memory devices, such as the synchronous dual port memory device 10 illustrated in FIG. 1, the address utilized for a read or write operation may be either an external address or an internally generated count which originates at a loaded address or a zero address. As is seen in FIG. 1, the dual port memory device 10 includes a memory array 12, I/O controls 14 and 14', input latches 18 and 18', drivers 20 and 20', read/write control latches 22 and 22', and NOR gates 24 and 24' which control the drivers 20 and 20' to activate during read operations, AND gates 26 and 26' which provide a read/write control signal to the I/O controls 14 and 14', chip enable control gates 28 and 28' and chip enable latches 30 and 30'.
Also provided are counter/address registers 16 and 16'. The counter/address registers 16 and 16' latch the address on the external address bus of the device for read and write operations and provide this address to the memory array 12. The counter/address registers 16 and 16' also provide an internally generated count to the memory array as an address. The count may be reset to 0 by the CNTRST signal and started by the signal CNTEN. The memory array 12 may then be sequentially accessed, beginning with an externally loaded address or 0 by incrementing the count.
FIG. 2 illustrates a possible circuit to carry out the functions of the counter/address registers 16 and 16'. As seen in FIG. 2, a multiplexer 32 receives the external address A.sub.0 -A.sub.15 as one input. The multiplexer 32 is controlled by the ADS signal so that when ADS is active, the multiplexer 32 outputs the external address. A second multiplexer 34 receives the output of the first multiplexer 32 and outputs either the output of the first multiplexer 32 or all 0's based on the signal CNTRST. If CNTRST is active, then all 0's are output and if CNTRST is inactive, then the output of the second multiplexer 34 is the output of the first multiplexer 32. The output of the second multiplexer 34 is provided to a counter/register 36 which stores the output of the multiplexer 34 on each cycle of CLK. The output of the counter/register 36 is provided to the memory array 12 and also provided to an adder 38 and a third multiplexer 40. The adder 38 increments the address value output by the counter/register 36 by 1 and provides that value to the third multiplexer 40. The third multiplexer 40 provides its output to the first multiplexer 32. The output of the third multiplexer 40 is controlled by the signal CNTEN to output the value of the counter/register 36 if CNTEN is inactive and the incremented value of the counter/register 36 if CNTEN is active.
A truth table for the address counter control is illustrated in Table 1.
TABLE 1 Address Counter Control Pre- Ad- vious dress Address CLK ADS CNTEN CNTRST I/O MODE X X .Arrow-up bold. H H L Dout Counter reset (0) to Address 0 An X .Arrow-up bold. L H H Dout External (n) Address Utilized X An .Arrow-up bold. H H H Dout External (n) Address Blocked - Counter disabled X An .Arrow-up bold. H L H Dout Counter (n+1) Enabled - Internal Address generation
As is seen in the above truth table and from the circuit illustrated in FIG. 2, the address may be reset to Address 0 but may not be reset to an externally loaded address. To restart a read or a write operation which utilized internal address generation at an address other than 0, a new address is loaded from the external address bus. Accordingly, an additional address cycle may be required to restart any non-zero operations. Thus, if a write operation is immediately followed by a read or a series of read operations from the same initial non-zero or intermediate starting address, the initial starting address will be loaded for each operation. Additional dual port memory devices having a loadable address for read operations are illustrated in U.S. Pat. No. 4,633,441.
In other devices, such as first-in-first-out (FIFO) buffers, internal addresses may be utilized to access memory. These pointers to memory may be utilized to track the sequence in which data is stored in memory to create a FIFO from a random access memory. In particular in FIFOs with a "fast retransmit mode," a read address may be stored and used as a mark to return to begin transmission. Typically, this read address does not correspond to an external address and the FIFO typically reads to this address and then sets a mark to begin retransmission. An example of such a FIFO is illustrated in U.S. Pat. No. 5,365,485.